This invention is related to methods for operating integrated circuit arrays of cross-point thyristor memory cells with MOS assist gates. In a general integrated circuit memory array, each memory cell, sometimes called bit cells, in an integrated circuit array holds, or stores, a bit of data, either a logic “1” or logic “0.” Data is retrieved from the memory cells of the array in a read operation and inserted into the memory cells for storage in a write operation.
The memory cells of an array are packed together on a semiconductor substrate which may cause problems in the read and write operations. In cross-point memory arrays of thyristor memory cells there are various disturbance problems, including the loss or corruption of data stored within unselected and half-selected bit cells. During write operations, the data in memory cells which are connected to a cell selected for read or write operations may be corrupted, sometimes termed as “disturbs” in the semiconductor technology field. That is, the data in the memory cells connected to the word line of the selected cell and/or the memory cells connected to the bit line of the selected cell might be disturbed by write operations performed on the selected memory cell such that the integrity of the stored data is compromised.
This invention is related to methods of operation for controlling the disturbances in the cross-point thyristor memory cell array to preserve the integrity of the stored data. The invention provides for the methods of carrying out operations and avoiding data disturbance in the thyristor memory cell array, including effective techniques for writing “1” into the array and for recovering “0” stored in the array to minimize the effects of disturbance.